In an amplifier circuit, it is often desirable for the output signal to have the freedom to swing “rail-to-rail” in operation, meaning that the output should be able to swing close to the upper “supply” voltage, sometimes called “V+” “VCC” or “VDD,” and the lower supply voltage, typically called “ground,” “V−,” “VSS,” or “VEE.” Additionally, it is often desirable that the output stage offer class-AB operation, meaning that the output signal current peak not be limited by the quiescent bias current.
In some applications, output stages having a single input terminal at an input DC voltage close to the supply are critical to the operation of the preceding stage. In the prior art, this may be achieved with a p-type common-gate input stage such as a p-type MOSFET (sometimes called a “pMOS”) cascode.
In some prior art amplifiers a signal current out of the cascode device directly controls the control terminal of an output device with no further delay due to non-dominant poles, which helps with high-frequency operation. However, to control the control terminal of the complementary output device, the signal may pass through a “Monticelli” mesh (so called because a mesh of this type was first proposed by Dennis Monticelli, “A Quad CMOS Single-Supply Op Amp with Rail-to-Rail Output Swing,” IEEE Journal of Solid-State Circuits, Vol. SC-21, Nol. 6, Dec. 1986, incorporated herein by reference). That signal may suffer additional delay. For example, an exemplary prior art device may include a pMOS cascode device with its output connected to the gate of an nMOS output device and a Monticelli mesh which has one terminal connected to that same point and the other terminal connected to the gate of a pMOS output device. For the electrical path that the signal follows to control the gate of the pMOS output device, the Monticelli mesh acts as an n-type cascode with a pole given by the 1/gm of the n-type device within the Monticelli mesh and the total capacitance at the node to which the gate of the nMOS output device is connected. The Monticelli mesh then acts as an additional stage contributing a non-dominant pole when the pMOS gate is driven. In some cases, this may provide additional delay for positive output signals.